Implementation of efficient SR-Latch PUF on FPGA and SoC devices.
Bilal HabibJens-Peter KapsKris GajPublished in: Microprocess. Microsystems (2017)
Keyphrases
- hardware implementation
- low power
- reconfigurable hardware
- electronic devices
- efficient implementation
- hardware architecture
- high speed
- complexity analysis
- highly optimized
- real time image processing
- computationally efficient
- single chip
- hardware architectures
- image sequences
- dedicated hardware
- hardware design
- field programmable gate array
- cost effective
- signal processing