Two-Symbol FPGA Architecture for Fast Arithmetic Encoding in JPEG 2000.
Nandini Ramesh KumarWei XiangYafeng WangPublished in: J. Signal Process. Syst. (2012)
Keyphrases
- fpga implementation
- pipelined architecture
- hardware implementation
- hardware design
- real time
- field programmable gate array
- hardware architecture
- image compression
- image coding
- parallel architecture
- high speed
- management system
- arithmetic coder
- decoding process
- software implementation
- fpga device
- xilinx virtex
- fpga technology
- jpeg compression
- compression algorithm
- signal processing
- hardware architectures
- fractal image compression
- dedicated hardware
- reconfigurable hardware
- systolic array
- compressed domain
- floating point arithmetic
- run length encoding
- coded images
- dct coefficients
- floating point
- low cost
- image processing