An interleaved cache clustered VLIW processor.
Enric GibertF. Jesús SánchezAntonio GonzálezPublished in: ICS (2002)
Keyphrases
- processor core
- embedded processors
- level parallelism
- memory hierarchy
- memory subsystem
- cache misses
- shared memory multiprocessors
- database workloads
- memory access
- shared memory multiprocessor
- multithreading
- memory bandwidth
- instruction set
- single chip
- cache management
- prefetching
- memory management
- main memory
- computer architecture
- computing power
- operating system
- hit rate
- ibm zenterprise
- parallel processing
- high speed
- industry standard
- database operations
- multiprocessor systems
- query processing
- data access
- parallel implementation
- input output
- database systems
- hierarchical structure
- hit ratio
- back end
- real time
- access patterns
- computational power