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A 1.8-GS/s 6-Bit Two-Step SAR ADC in 65-nm CMOS.
Xiangyu Meng
Weihao Kong
Haifeng Yang
Yecong Li
Xuan Li
Published in:
ISCAS (2021)
Keyphrases
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analog to digital converter
nm technology
random access memory
high speed
image reconstruction
low power
cmos technology
power consumption
low cost
multiscale
parameter estimation
synthetic aperture radar
silicon on insulator
post processing
vlsi circuits