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A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS.

Kwanseo ParkWoo-Rham BaeJinhyung LeeJeongho HwangDeog-Kyoon Jeong
Published in: IEEE J. Solid State Circuits (2018)
Keyphrases
  • high speed
  • random access memory
  • image processing
  • analog vlsi
  • database
  • machine learning
  • genetic algorithm
  • learning algorithm
  • feedback loop