A hardware-friendly algorithm for scalable training and deployment of dimensionality reduction models on FPGA.
Mahdi NazemiAmir Erfan EshratifarMassoud PedramPublished in: ISQED (2018)
Keyphrases
- single pass
- fpga implementation
- learning algorithm
- memory efficient
- objective function
- hardware implementation
- detection algorithm
- np hard
- probabilistic model
- real time
- training phase
- high speed
- fpga device
- hardware architecture
- dimensionality reduction
- low cost
- k means
- computational complexity
- neural network
- expectation maximization
- software implementation
- data sets