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A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations.
Claudio Brunelli
Fabio Garzia
Davide Rossi
Jari Nurmi
Published in:
J. Syst. Archit. (2010)
Keyphrases
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floating point
coarse grain
reconfigurable architecture
fine grain
fixed point
systolic array
instruction set
parallel computation
distributed memory
general purpose
pairwise
higher order
response time
multithreading