Low-power dual-supply clock networks with clock gating and frequency doubling.
Hoi-Jin LeeJong-Woo KimTae Hee HanJae-Cheol SonJeong-Taek KongBai-Sun KongPublished in: IEICE Electron. Express (2012)
Keyphrases
- power consumption
- low power
- clock gating
- power reduction
- power dissipation
- high speed
- energy efficiency
- power saving
- low power consumption
- single chip
- logic circuits
- energy saving
- low cost
- network structure
- digital signal processing
- cmos technology
- vlsi architecture
- data center
- image restoration
- real time
- signal processing
- mixed signal
- gate array