A 1.4-psec Jitter 2.5-Gb/s CDR with wide acquisition range in 0.18-μm CMOS.

M. Kumarasamy Raja Dan Lei Yan Aruna B. Ajjikuttira

Published in: ESSCIRC (2007)

Keyphrases

high speed
wide range
low cost
power consumption
data acquisition
circuit design
neural network
motion estimation
database
data sets
time of flight
delay insensitive
analog vlsi