Area-Optimized Constant-Time Hardware Implementation for Polynomial Multiplication.
Safiullah KhanWai-Kong LeeAyesha KhalidAbdul MajeedSeong Oun HwangPublished in: IEEE Embed. Syst. Lett. (2023)
Keyphrases
- pattern recognition
- hardware implementation
- signal processing
- efficient implementation
- software implementation
- image processing algorithms
- machine learning
- dedicated hardware
- fpga implementation
- neural network
- hardware design
- memory management
- field programmable gate array
- hardware architecture
- floating point
- pipeline architecture
- power consumption
- general purpose
- image binarization