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Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding.
Rizwan Asghar
Di Wu
Johan Eilert
Dake Liu
Published in:
J. Signal Process. Syst. (2010)
Keyphrases
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real time
data analysis
parallel architecture
neural network
management system
layered architecture
error correction
parallel implementation
design considerations
architectural design
platform independent
hardware architecture
level parallelism