A novel fault-tolerant router architecture for network-on-chip reconfiguration.

Pengzhan Yan Shixiong Jiang Ramalingam Sridhar

Published in: SoCC (2015)

Keyphrases

network on chip
fault tolerant
interconnection networks
fault tolerance
multi processor
routing algorithm
packet switched
distributed systems
network simulator
data transfer
program execution
ad hoc networks
load balancing
shared memory
shortest path
real time
multistage