Input Elimination and Abstraction in Model Checking.
Sela Mador-HaimLimor FixPublished in: FMCAD (1998)
Keyphrases
- model checking
- temporal logic
- bounded model checking
- finite state
- model checker
- formal verification
- temporal properties
- formal specification
- automated verification
- finite state machines
- partial order reduction
- timed automata
- computation tree logic
- verification method
- process algebra
- transition systems
- epistemic logic
- formal methods
- pspace complete
- linear temporal logic
- symbolic model checking
- concurrent systems
- reachability analysis
- reactive systems
- alternating time temporal logic
- asynchronous circuits
- linear time temporal logic
- satisfiability problem