Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique.
Kazunori ShimizuNozomu TogawaTakeshi IkenagaSatoshi GotoPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2008)
Keyphrases
- low density parity check
- low power
- vlsi architecture
- ldpc codes
- error correction
- decoding algorithm
- image transmission
- channel coding
- high speed
- low cost
- power consumption
- distributed video coding
- image compression
- message passing
- low complexity
- vlsi implementation
- channel capacity
- compression algorithm
- rate allocation
- compression ratio
- physical layer
- real time
- mixed signal
- compressed images
- turbo codes
- nm technology
- cmos technology
- error resilience
- data flow
- bit error rate
- error propagation