Doubling FPGA Throughput via a Soft SerDes Architecture for Full-Bandwidth Serial Pipelining (Abstract Only).
Aaron LandyGreg StittPublished in: FPGA (2016)
Keyphrases
- hardware implementation
- hardware architecture
- dedicated hardware
- hardware design
- response time
- fpga implementation
- real time
- pipelined architecture
- high speed
- software implementation
- buffer size
- field programmable gate array
- high level
- hardware architectures
- parallel architecture
- low latency
- management system
- xilinx virtex
- fpga technology
- congestion control
- high bandwidth
- network bandwidth
- single chip
- resource utilization
- computational power
- associative memory
- channel capacity
- reconfigurable hardware
- end to end