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Breaking the Circuit-Size Barrier for Secure Computation under Quasi-Polynomial LPN.
Geoffroy Couteau
Pierre Meyer
Published in:
IACR Cryptol. ePrint Arch. (2021)
Keyphrases
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high speed
real time
computational complexity
lightweight
memory requirements
standard deviation
maximum number
polynomial size
electronic circuits
low cost
efficient computation
low order
analog circuits