An FPGA systolic array using pseudo-random bit generators for computing Goldbach partitions.

Dominique Lavenier

Published in: Integr. (2000)

Keyphrases

systolic array
pseudorandom
random numbers
reconfigurable architecture
uniformly distributed
data flow
random number
parallel architecture
secret key
high speed
data sets
user specific
pattern recognition
database systems
high dimensional data
hardware implementation
dimensionality reduction
low cost
data model