Power and chip-area aware network-on-chip modeling for system on chip simulation.
Masoud Oveis GharanGul N. KhanPublished in: SimuTools (2014)
Keyphrases
- network on chip
- power consumption
- power dissipation
- network simulator
- packet switched
- routing algorithm
- chip design
- low power
- cmos technology
- high speed
- design methodology
- multi processor
- simulation model
- single chip
- hardware and software
- low cost
- simulation environment
- data transfer
- mobile ad hoc networks
- shortest path
- ibm power processor