Login / Signup

Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.

Kumar YelamarthiChien-In Henry Chen
Published in: J. Comput. (2008)
Keyphrases
  • load balance
  • high speed
  • multiple paths
  • real time
  • computational complexity
  • low cost
  • intelligent agents
  • resource allocation
  • scheduling algorithm
  • joint optimization