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A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck.
Claudio Brunelli
Fabio Garzia
Carmelo Giliberto
Jari Nurmi
Published in:
FPL (2008)
Keyphrases
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main memory
data sets
memory usage
multi valued
logic programming
memory requirements
memory space
random access memory
artificial intelligence
data structure
high speed
expressive power
significantly reduced
classical logic
computational properties