Fast Hardware Architecture for 2-D Separable Convolution Operations.
Debasish MukherjeeSusanta MukhopadhyayPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2018)
Keyphrases
- hardware architecture
- processing elements
- hardware implementation
- hardware architectures
- matrix multiplication
- associative memory
- field programmable gate array
- signal processing
- image processing
- data processing
- neural network
- image processing algorithms
- massively parallel
- feature vectors
- feature extraction
- artificial intelligence
- genetic algorithm