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Implementing precise interruptions in pipelined RISC processors.
Chia-Jiu Wang
Frank Emnett
Published in:
IEEE Micro (1993)
Keyphrases
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instruction set
parallel architecture
parallel processing
instruction set architecture
application specific
parallel algorithm
floating point
data flow
shared memory
parallel computation
computer architecture
highly accurate
general purpose
data sets
high end
communication delays
learning algorithm