Constant-Time Loading: Modifying CPU Pipeline to Defeat Cache Side-Channel Attacks.
Yusi FengZiyuan ZhuShuan LiBen LiuHuozhu WangDan MengPublished in: TrustCom (2021)
Keyphrases
- cache misses
- memory hierarchy
- memory access
- multithreading
- main memory
- prefetching
- computing power
- smart card
- pipeline architecture
- introducing additional
- hit rate
- processing pipeline
- query processing
- data access
- cache management
- personal computer
- external memory
- back end
- secondary storage
- virtual memory
- highly efficient
- computer architecture
- computational power
- hit ratio
- caching scheme
- memory bandwidth
- embedded processors
- database management systems
- data transfer