A high performance VLSI architecture for integer motion estimation in HEVC.
Yuan XuJinsong LiuLiwei GongZhi ZhangRobert K. F. TengPublished in: ASICON (2013)
Keyphrases
- vlsi architecture
- motion estimation
- low complexity
- video compression
- video coding
- motion compensation
- image sequences
- video sequences
- computational complexity
- motion vectors
- motion compensated
- optical flow
- spatial domain
- reference frame
- motion field
- computer vision
- inter frame
- real time
- mode decision
- coding efficiency
- super resolution
- rate distortion
- bit plane
- video codec
- distributed video coding
- vlsi implementation
- low power
- transform domain
- high speed
- video coding standard
- video quality