Low power pulsed flip-flop with clock gating and conditional pulse enhancement.

Kuruvilla John R. S. Vinod Kumar S. S. Kumar

Published in: Int. J. Autom. Control. (2021)

Keyphrases

power dissipation
low power
flip flops
power consumption
high speed
low cost
power reduction
digital signal processing
cmos technology
logic circuits
image enhancement
low power consumption
energy efficiency
real time
image sensor
ultra low power
image processing