Mapping for better than worst-case delays in LUT-based FPGA designs.
Kirill MinkovichJason CongPublished in: FPGA (2008)
Keyphrases
- worst case
- lower bound
- upper bound
- high speed
- real time image processing
- average case
- error bounds
- np hard
- greedy algorithm
- field programmable gate array
- real time
- low cost
- hardware design
- inverse halftoning
- software implementation
- round trip
- systolic array
- low power consumption
- fpga technology
- running times
- approximation algorithms
- signal processing
- digital images
- special case