A DVS-based pipelined reconfigurable instruction memory.
Zhiguo GeTulika MitraWeng-Fai WongPublished in: DAC (2009)
Keyphrases
- memory hierarchy
- low cost
- reconfigurable architecture
- level parallelism
- instruction set architecture
- instruction set
- computing power
- general purpose
- main memory
- multimedia
- memory usage
- scheduling algorithm
- memory requirements
- neural network
- computational power
- computer architecture
- instructional design
- random access
- working memory
- memory size
- data flow
- secondary storage
- hardware implementation
- cache misses
- linear array
- learning disabled students
- speculative execution