Dynamically Reconfigurable Architecture for Fault-Tolerant 2D Networks-on-Chip.
Poona BahrebarAzarakhsh JalalvandDirk StroobandtPublished in: ICCCN (2017)
Keyphrases
- fault tolerant
- fault tolerance
- interconnection networks
- distributed systems
- network on chip
- evolvable hardware
- load balancing
- high speed
- analog vlsi
- high bandwidth
- vlsi implementation
- social networks
- safety critical
- high availability
- low cost
- state machine
- host computer
- functional units
- level parallelism
- mobile agent system
- operating system
- response time
- multimedia