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A design of HTM spatial pooler for face recognition using memristor-CMOS hybrid circuits.

Timur IbrayevAlex Pappachen JamesCory E. MerkelDhireesha Kudithipudi
Published in: ISCAS (2016)
Keyphrases
  • circuit design
  • high speed
  • delay insensitive
  • chip design
  • high level synthesis
  • single chip
  • power dissipation
  • vlsi circuits
  • artificial neural networks
  • evolutionary algorithm
  • power consumption
  • cmos technology