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17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI.

Mahmood KhayatzadehMehdi SaliganeJingcheng WangMassimo AliotoDavid T. BlaauwDennis Sylvester
Published in: ISSCC (2016)
Keyphrases
  • error detection and correction
  • error correction
  • data transmission
  • low cost
  • memory requirements
  • real time
  • power reduction