Funktionale und quantitative Verifikation von zeit- und ressourcenerweiterten SDL-Systemen mittels Model-Checking.
Marc DiefenbruchPublished in: MMB (1997)
Keyphrases
- model checking
- temporal logic
- formal verification
- automated verification
- finite state
- temporal properties
- finite state machines
- model checker
- partial order reduction
- formal specification
- verification method
- timed automata
- symbolic model checking
- reachability analysis
- computation tree logic
- epistemic logic
- concurrent systems
- transition systems
- bounded model checking
- formal methods
- asynchronous circuits
- artificial intelligence
- deterministic finite automaton
- alternating time temporal logic
- process algebra
- satisfiability problem
- abstract interpretation
- software engineering