Login / Signup
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads.
Hiroaki Hirata
Kozo Kimura
Satoshi Nagamine
Yoshiyuki Mochizuki
Akio Nishimura
Yoshimori Nakase
Teiji Nishizawa
Published in:
ISCA (1992)
Keyphrases
</>
level parallelism
instruction set
memory hierarchy
computer architecture
industry standard
parallel processing
memory management
neural network
management system
computer technology
multi processor
computation intensive