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A Parallel Yet Pipelined Architecture for Efficient Implementation of the Advanced Encryption Standard Algorithm on Reconfigurable Hardware.
Nadia Nedjah
Luiza de Macedo Mourelle
Chao Wang
Published in:
Int. J. Parallel Program. (2016)
Keyphrases
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efficient implementation
hardware implementation
pipelined architecture
image processing algorithms
parallel implementation
real time
np hard
low cost
signal processing
parallel architecture