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Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction Characteristics.
Daniel H. Morris
Uygar E. Avci
Rafael Rios
Ian A. Young
Published in:
IEEE J. Emerg. Sel. Topics Circuits Syst. (2014)
Keyphrases
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logic circuits
low voltage
gate array
low power
functional decomposition
pattern recognition
design considerations
power dissipation