A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder.
Pasquale CiaoGiulio ColavolpeLuca FanucciPublished in: DSD (2004)
Keyphrases
- vlsi architecture
- low complexity
- low density parity check
- turbo codes
- low power
- channel coding
- distributed video coding
- vlsi implementation
- rate allocation
- ldpc codes
- real time
- high speed
- error correction
- computational complexity
- parallel computing
- power consumption
- low cost
- motion estimation
- bit plane
- mode decision
- coding scheme
- bit errors