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A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme.
Daeyeon Kim
Gregory K. Chen
Matthew Fojtik
Mingoo Seok
David T. Blaauw
Dennis Sylvester
Published in:
ISCAS (2011)
Keyphrases
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high speed
random access memory
low power
protection scheme
real time
sensor networks
power consumption
data transmission
high levels
bit string