Triggering Optimization on NAND ESD Clamp and Its ESD Protection IO Scheme for CMOS Designs.

Jian Liu Divya Acharya Nathaniel Peachey

Published in: IRPS (2020)

Keyphrases

protection scheme
optimization scheme
high speed
global optimization
optimization problems
optimization algorithm
low cost
power consumption
optimization process
parallel processing
constrained optimization
optimization method
information security
highly efficient
cmos technology
cmos image sensor