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FeFET-based Process-in-Memory Architecture for Low-Power DNN Training.

Farzaneh ZokaeeBing LiFan Chen
Published in: NANOARCH (2021)
Keyphrases
  • low power
  • training process
  • high speed
  • power consumption
  • low cost
  • vlsi architecture
  • nm technology
  • single chip
  • cmos technology
  • general purpose
  • digital signal processing
  • high power