Design of Low Power Gain-Cell eDRAM for 4Kb Memory Array in 130nm CMOS.
Shi Rong SooAfiq HamzahNurul Ezaila AliasIzam KamisianMichael Loong Peng TanSuhaila IsaakZaharah JohariPublished in: ICEEI (2021)
Keyphrases
- low power
- cmos technology
- nm technology
- power consumption
- power dissipation
- single chip
- low cost
- high speed
- analog to digital converter
- vlsi architecture
- mixed signal
- low power consumption
- image sensor
- ultra low power
- vlsi circuits
- power reduction
- digital signal processing
- logic circuits
- high power
- knowledge base
- low voltage
- wireless transmission
- gate array
- dynamic range
- delay insensitive
- cmos image sensor
- hardware and software