Low power design techniques for nanometer design processes: 65 nm and smaller.
Subhomoy ChattopadhyayPublished in: SBCCI (2007)
Keyphrases
- low power
- design processes
- cmos technology
- design process
- single chip
- power consumption
- low power consumption
- high speed
- low cost
- nm technology
- engineering design
- digital signal processing
- logic circuits
- power reduction
- design decisions
- design methodology
- gate array
- expert systems
- vlsi circuits
- ultra low power
- vlsi architecture
- design theory
- power dissipation
- user interface
- design solutions