Packing Directed Circuits through Prescribed Vertices Bounded Fractionally.

Naonori Kakimura Ken-ichi Kawarabayashi

Published in: SIAM J. Discret. Math. (2012)

Keyphrases

high speed
truth table
packing problem
neural network
vlsi circuits
analog circuits
logic synthesis
search algorithm
weighted graph
power reduction
delay insensitive
strip packing
database
high level synthesis
analog vlsi
quantum computing
infrared
real time