Reconfigurable Traffic-Aware Radio Interconnect for a 2048-core Chip Multiprocessor.
Eren UnluChristophe MoyPublished in: DSD (2015)
Keyphrases
- high speed
- low cost
- network on chip
- power dissipation
- interconnection networks
- network traffic
- low power
- single chip
- highly parallel
- traffic flow
- multithreading
- level parallelism
- analog vlsi
- real time
- power reduction
- reconfigurable architecture
- hardware implementation
- wireless communication
- reconfigurable hardware
- network layer
- fault tolerant
- functional units
- power consumption