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A mixed PLL/DLL architecture for low jitter clock generation.
Yong-Cheol Bae
Gu-Yeon Wei
Published in:
ISCAS (4) (2004)
Keyphrases
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high levels
software architecture
case study
management system
layered architecture
generation process
databases
real time
optimal solution
search algorithm
database systems
high speed
website
associative memory
packet loss
network architecture
database