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Low-Power AES Data Encryption Architecture for a LoRaWAN.
Kun-Lin Tsai
Fang-Yie Leu
Ilsun You
Shuo-Wen Chang
Shiung-Jie Hu
Hoonyong Park
Published in:
IEEE Access (2019)
Keyphrases
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low power
data encryption
vlsi architecture
high speed
low cost
power consumption
encryption algorithms
encryption algorithm
single chip
nm technology
cmos technology
mixed signal
logic circuits
real time
low power consumption
image sensor
secret key
vlsi implementation
data confidentiality
data quality