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Combining DEVS and model-checking: concepts and tools for integrating simulation and analysis.
Bernard P. Zeigler
James J. Nutaro
Chungman Seo
Published in:
Int. J. Simul. Process. Model. (2017)
Keyphrases
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model checking
temporal logic
dynamic analysis
formal methods
formal specification
temporal properties
formal verification
partial order reduction
description logics
model checker
epistemic logic
pspace complete
asynchronous circuits
reachability analysis