10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter.
Dingxin XuZezheng LiuYifeng KuaiHongye HuangYuncheng ZhangZheng SunBangan LiuWenqian WangYuang XiongJunjun QiuWaleed MadanyYi ZhangAshbir Aviat FadilaAtsushi ShiraneKenichi OkadaPublished in: ISSCC (2024)