Δ ∑ Time-to-Digital Converter Implemented on 40 nm Altera Stratix IV FPGA.
Ahmad Mouri Zadeh KhakiEbrahim FarshidiKarim Ansari-AslSawal Hamid Md. AliMasuri OthmanPublished in: IEEE Access (2021)
Keyphrases
- field programmable gate array
- hardware implementation
- fpga device
- pipelined architecture
- fpga technology
- programmable logic
- hardware design
- reconfigurable hardware
- software implementation
- fpga hardware
- embedded systems
- parallel computing
- computing systems
- hardware architecture
- fpga implementation
- data conversion
- image processing algorithms
- digital signal processing
- transfer function
- high speed
- image processing
- massively parallel
- analog to digital converter
- neural network
- hardware software
- low power consumption
- low cost