Asymmetric Prefetching Architecture for Multicore Processor.
Duheon ChoiKwangsu KimEui-Young ChungPublished in: ISOCC (2020)
Keyphrases
- prefetching
- response time
- memory management
- access patterns
- access latency
- level parallelism
- web prefetching
- memory access
- caching scheme
- cache misses
- hit rate
- web documents
- user perceived latency
- hit ratio
- web caching
- instruction set
- cache replacement
- parallel processing
- cell processor
- multiprocessor systems
- shared memory
- multi core processors
- web logs
- operating system
- multithreading
- web page prediction
- web objects
- web usage mining
- computing systems
- computer systems
- information extraction