32.5 A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/μs Slope.
Zhengkun ShenHaoyun JiangFan YangYixiao WangZherui ZhangJunhua LiuHuailin LiaoPublished in: ISSCC (2021)
Keyphrases
- clock frequency
- dielectric constant
- power consumption
- high speed
- user friendly
- simulation software
- phase locked loop
- electric field
- field programmable gate array
- low power
- high end
- parallel architecture
- frequency band
- parallel computing
- fourier transform
- frequency domain
- low frequency
- intel xeon
- microstrip
- multi view
- root mean square
- patch antenna
- expert systems
- signal processing
- space variant
- hardware implementation