Low power low leakage clock gated static pulsed flip-flop.
A. S. SeyediS. H. RasouliAmir AmirabadiAli Afzali-KushaPublished in: ISCAS (2006)
Keyphrases
- low power
- power consumption
- high speed
- power dissipation
- low power consumption
- cmos technology
- flip flops
- low cost
- single chip
- high power
- wireless transmission
- vlsi circuits
- logic circuits
- digital signal processing
- power saving
- vlsi architecture
- real time
- gate array
- delay insensitive
- power reduction
- pattern recognition
- image sensor
- nm technology